As is well known, conventional PLL circuits are often used to lock an oscillator, such as a voltage controlled oscillator (VCO), to a reference signal. One problem associated with such circuits is phase noise (i.e., jitter) exhibited on the output signal generated by the VCO.
In one approach, to reduce such jitter, the VCO may be implemented with a relatively low gain. As a result, a change in the VCO's control voltage will cause only a modest change in output signal frequency. Unfortunately, this approach can reduce the usable frequency range of the VCO.
In another approach, a PLL circuit may be implemented with a VCO having two input paths for receiving signals from two analog tuning loops. The first input path may apply a high gain to a first control signal received from the first analog tuning loop to perform a fast coarse tuning of the VCO. The second input path may apply a low gain to a second control signal received from the second analog tuning loop to perform a slow fine tuning of the VCO. Unfortunately, this approach requires complex analog circuitry and involves additional loop dynamics in comparison to more conventional PLL circuits. As a result, there is a need for an improved PLL circuit implementation.